The present invention relates, in general, to electronics and, more particularly, to methods of forming semiconductors.
In the past, the semiconductor industry utilized various methods and equipment to singulate individual semiconductor die from a semiconductor wafer on which the die was manufactured. Typically, a technique called scribing or dicing was used to either partially or fully cut through the wafer with a diamond cutting wheel along scribe grids or singulation lines that were formed on the wafer between the individual die. To allow for the alignment and the width of the dicing wheel each scribe grid usually had a large width, generally about one hundred fifty (150) microns, which consumed a large portion of the semiconductor wafer. Additionally, the time required to scribe each singulation line on the semiconductor wafer could take over one hour or more. This time reduced the throughput and manufacturing capacity of a production facility.
Other methods, which have included thermal laser separation (TLS), stealth dicing (laser dicing from the backside of the wafer), and plasma dicing, have been explored as alternatives to scribing. Plasma dicing is a promising process compared to scribing and other alternative processes because it supports narrower scribe lines, has increased throughput, and can singulate die in varied and flexible patterns. However, plasma dicing has had manufacturing implementation challenges. Such challenges have included non-compatibility with wafer backside layers, such as backmetal layers, because the etch process has been unable to effectively remove the backside layers from the singulation lines. Removing the backside layers from the scribe lines is necessary to facilitate subsequent processing, such as pick-and-place and assembly processes.
Accordingly, it is desirable to have a method of singulating die from a semiconductor wafer that separates the backside layers from within the singulation lines. It would be beneficial for the method to be cost effective, to minimize any damage to or contamination of the separated die, and to support reclaim efforts.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles. Furthermore, the term “major surface” when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.